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[/] [or1k/] [tags/] [rel_15/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7993d 14h /or1k/tags/rel_15/
993 Fixed IMMU bug. lampret 7993d 14h /or1k/tags/rel_15/
992 A bug when cache enabled and bus error comes fixed. simons 7993d 23h /or1k/tags/rel_15/
991 Different memory controller. simons 7993d 23h /or1k/tags/rel_15/
990 Test is now complete. simons 7993d 23h /or1k/tags/rel_15/
989 c++ is making problems so, for now, it is excluded. simons 7995d 07h /or1k/tags/rel_15/
988 ORP architecture supported. simons 7995d 22h /or1k/tags/rel_15/
987 ORP architecture supported. simons 7996d 06h /or1k/tags/rel_15/
986 outputs out of function are not registered anymore markom 7996d 06h /or1k/tags/rel_15/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7996d 18h /or1k/tags/rel_15/
984 Disable SB until it is tested lampret 7996d 18h /or1k/tags/rel_15/
983 First checkin lampret 7996d 20h /or1k/tags/rel_15/
982 Moved to sim/bin lampret 7996d 20h /or1k/tags/rel_15/
981 First checkin. lampret 7996d 20h /or1k/tags/rel_15/
980 Removed sim.tcl that shouldn't be here. lampret 7996d 20h /or1k/tags/rel_15/
979 Removed old test case binaries. lampret 7996d 20h /or1k/tags/rel_15/
978 Added variable delay for SRAM. lampret 7996d 20h /or1k/tags/rel_15/
977 Added store buffer. lampret 7996d 20h /or1k/tags/rel_15/
976 Added store buffer lampret 7996d 20h /or1k/tags/rel_15/
975 First checkin lampret 7996d 20h /or1k/tags/rel_15/

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