OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] - Rev 1131

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7759d 11h /or1k/tags/rel_15/or1200/rtl/
1130 RFRAM type always need to be defined. lampret 7759d 11h /or1k/tags/rel_15/or1200/rtl/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7759d 11h /or1k/tags/rel_15/or1200/rtl/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7834d 09h /or1k/tags/rel_15/or1200/rtl/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7879d 04h /or1k/tags/rel_15/or1200/rtl/
1083 SB mem width fixed. simons 7910d 23h /or1k/tags/rel_15/or1200/rtl/
1079 RAMs wrong connected to the BIST scan chain. mohor 7919d 20h /or1k/tags/rel_15/or1200/rtl/
1078 Previous check-in was done by mistake. mohor 7919d 21h /or1k/tags/rel_15/or1200/rtl/
1077 Signal scanb_sen renamed to scanb_en. mohor 7919d 21h /or1k/tags/rel_15/or1200/rtl/
1069 Signal scanb_eni renamed to scanb_en mohor 7923d 14h /or1k/tags/rel_15/or1200/rtl/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7930d 16h /or1k/tags/rel_15/or1200/rtl/
1055 Removed obsolete comment. lampret 7962d 09h /or1k/tags/rel_15/or1200/rtl/
1054 Fixed a combinational loop. lampret 7962d 09h /or1k/tags/rel_15/or1200/rtl/
1053 Disabled cache inhibit atttribute. lampret 7962d 09h /or1k/tags/rel_15/or1200/rtl/
1038 Fixed a typo, reported by Taylor Su. lampret 7969d 17h /or1k/tags/rel_15/or1200/rtl/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7970d 07h /or1k/tags/rel_15/or1200/rtl/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7970d 17h /or1k/tags/rel_15/or1200/rtl/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7971d 07h /or1k/tags/rel_15/or1200/rtl/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7974d 12h /or1k/tags/rel_15/or1200/rtl/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7974d 14h /or1k/tags/rel_15/or1200/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.