URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] - Rev 1023

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	7987d 20h	/or1k/tags/rel_15/or1200/rtl/verilog/
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	7987d 22h	/or1k/tags/rel_15/or1200/rtl/verilog/
1011	Removed some commented RTL. Fixed SR/ESR flag bug.	lampret	7994d 19h	/or1k/tags/rel_15/or1200/rtl/verilog/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	8000d 18h	/or1k/tags/rel_15/or1200/rtl/verilog/
993	Fixed IMMU bug.	lampret	8000d 18h	/or1k/tags/rel_15/or1200/rtl/verilog/
984	Disable SB until it is tested	lampret	8003d 23h	/or1k/tags/rel_15/or1200/rtl/verilog/
977	Added store buffer.	lampret	8004d 01h	/or1k/tags/rel_15/or1200/rtl/verilog/
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8007d 15h	/or1k/tags/rel_15/or1200/rtl/verilog/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8008d 14h	/or1k/tags/rel_15/or1200/rtl/verilog/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8010d 15h	/or1k/tags/rel_15/or1200/rtl/verilog/
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8010d 15h	/or1k/tags/rel_15/or1200/rtl/verilog/
942	Delayed external access at page crossing.	lampret	8010d 15h	/or1k/tags/rel_15/or1200/rtl/verilog/
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8022d 19h	/or1k/tags/rel_15/or1200/rtl/verilog/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8038d 22h	/or1k/tags/rel_15/or1200/rtl/verilog/
871	Generic flip-flop based memory macro for register file.	lampret	8075d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8075d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/
869	Added generic flip-flop based memory macro instantiation.	lampret	8075d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8146d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/
794	Added again just recently removed full_case directive	lampret	8146d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8146d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] - Rev 1023

Filtering Options