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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] - Rev 573

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Rev Log message Author Age Path
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8209d 06h /or1k/tags/rel_16/or1200/rtl/verilog/
571 Changed alignment exception EPCR. Not tested yet. lampret 8209d 15h /or1k/tags/rel_16/or1200/rtl/verilog/
570 Fixed order of syscall and range exceptions. lampret 8209d 17h /or1k/tags/rel_16/or1200/rtl/verilog/
569 Default ASIC configuration does not sample WB inputs. lampret 8210d 02h /or1k/tags/rel_16/or1200/rtl/verilog/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8210d 06h /or1k/tags/rel_16/or1200/rtl/verilog/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8216d 11h /or1k/tags/rel_16/or1200/rtl/verilog/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8220d 14h /or1k/tags/rel_16/or1200/rtl/verilog/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8221d 04h /or1k/tags/rel_16/or1200/rtl/verilog/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8251d 07h /or1k/tags/rel_16/or1200/rtl/verilog/
401 *** empty log message *** simons 8254d 17h /or1k/tags/rel_16/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8254d 17h /or1k/tags/rel_16/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8254d 17h /or1k/tags/rel_16/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8257d 13h /or1k/tags/rel_16/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8257d 14h /or1k/tags/rel_16/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8257d 16h /or1k/tags/rel_16/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8257d 16h /or1k/tags/rel_16/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8261d 14h /or1k/tags/rel_16/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8262d 03h /or1k/tags/rel_16/or1200/rtl/verilog/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8262d 22h /or1k/tags/rel_16/or1200/rtl/verilog/
360 Added OR1200_REGISTERED_INPUTS. lampret 8264d 14h /or1k/tags/rel_16/or1200/rtl/verilog/

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