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[/] [or1k/] [tags/] [rel_17/] [or1200/] - Rev 1131

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Rev Log message Author Age Path
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7736d 05h /or1k/tags/rel_17/or1200/
1130 RFRAM type always need to be defined. lampret 7736d 05h /or1k/tags/rel_17/or1200/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7736d 05h /or1k/tags/rel_17/or1200/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7811d 03h /or1k/tags/rel_17/or1200/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7855d 21h /or1k/tags/rel_17/or1200/
1083 SB mem width fixed. simons 7887d 16h /or1k/tags/rel_17/or1200/
1079 RAMs wrong connected to the BIST scan chain. mohor 7896d 14h /or1k/tags/rel_17/or1200/
1078 Previous check-in was done by mistake. mohor 7896d 15h /or1k/tags/rel_17/or1200/
1077 Signal scanb_sen renamed to scanb_en. mohor 7896d 15h /or1k/tags/rel_17/or1200/
1069 Signal scanb_eni renamed to scanb_en mohor 7900d 08h /or1k/tags/rel_17/or1200/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7907d 10h /or1k/tags/rel_17/or1200/
1055 Removed obsolete comment. lampret 7939d 03h /or1k/tags/rel_17/or1200/
1054 Fixed a combinational loop. lampret 7939d 03h /or1k/tags/rel_17/or1200/
1053 Disabled cache inhibit atttribute. lampret 7939d 03h /or1k/tags/rel_17/or1200/
1040 Updated the script. lampret 7946d 09h /or1k/tags/rel_17/or1200/
1039 Added linter directory. lampret 7946d 09h /or1k/tags/rel_17/or1200/
1038 Fixed a typo, reported by Taylor Su. lampret 7946d 11h /or1k/tags/rel_17/or1200/
1037 First import of the new synopsys DC scripts. lampret 7946d 11h /or1k/tags/rel_17/or1200/
1036 Removed old synthesis scripts. lampret 7946d 11h /or1k/tags/rel_17/or1200/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7947d 00h /or1k/tags/rel_17/or1200/

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