OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_18/] - Rev 1077

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1077 Signal scanb_sen renamed to scanb_en. mohor 7953d 19h /or1k/tags/rel_18/
1076 channels integration rprescott 7954d 12h /or1k/tags/rel_18/
1075 channels integration rprescott 7954d 12h /or1k/tags/rel_18/
1074 channels integration rprescott 7954d 12h /or1k/tags/rel_18/
1073 channels support rprescott 7956d 15h /or1k/tags/rel_18/
1072 Added me ;-) rprescott 7956d 15h /or1k/tags/rel_18/
1070 Channels (fd,file,xterm) first import rprescott 7956d 16h /or1k/tags/rel_18/
1069 Signal scanb_eni renamed to scanb_en mohor 7957d 11h /or1k/tags/rel_18/
1068 Minimum packet length cheching changed to present the real hw. simons 7958d 08h /or1k/tags/rel_18/
1067 Changed main structure. rherveille 7961d 00h /or1k/tags/rel_18/
1066 readme updated markom 7961d 00h /or1k/tags/rel_18/
1065 Removed trailing ' \' used to continue code on the next line.
This caused problems with some compilers.
rherveille 7963d 21h /or1k/tags/rel_18/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7964d 14h /or1k/tags/rel_18/
1062 few cuc bugs fixed markom 7970d 23h /or1k/tags/rel_18/
1061 ELF sym loading improved markom 7971d 19h /or1k/tags/rel_18/
1060 cuc sw loading bug fixed markom 7984d 19h /or1k/tags/rel_18/
1059 several cuc bugs fixed; different verilog cuc file naming markom 7984d 19h /or1k/tags/rel_18/
1058 Different memory controller. simons 7995d 13h /or1k/tags/rel_18/
1057 Different memory controller. simons 7995d 13h /or1k/tags/rel_18/
1055 Removed obsolete comment. lampret 7996d 06h /or1k/tags/rel_18/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.