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[/] [or1k/] [tags/] [rel_2/] [or1200/] [rtl/] - Rev 870

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870 Added defines for enabling generic FF based memory macro for register file. lampret 8045d 20h /or1k/tags/rel_2/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8045d 20h /or1k/tags/rel_2/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8116d 20h /or1k/tags/rel_2/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8116d 20h /or1k/tags/rel_2/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8116d 20h /or1k/tags/rel_2/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8116d 20h /or1k/tags/rel_2/or1200/rtl/
788 Some of the warnings fixed. lampret 8116d 21h /or1k/tags/rel_2/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8117d 17h /or1k/tags/rel_2/or1200/rtl/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8117d 17h /or1k/tags/rel_2/or1200/rtl/
776 Updated defines. lampret 8117d 17h /or1k/tags/rel_2/or1200/rtl/
775 Optimized cache controller FSM. lampret 8117d 17h /or1k/tags/rel_2/or1200/rtl/
774 Removed old files. lampret 8117d 18h /or1k/tags/rel_2/or1200/rtl/
737 Added alternative for critical path in DU. lampret 8132d 12h /or1k/tags/rel_2/or1200/rtl/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8135d 11h /or1k/tags/rel_2/or1200/rtl/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8135d 11h /or1k/tags/rel_2/or1200/rtl/
668 Lapsus fixed. simons 8159d 21h /or1k/tags/rel_2/or1200/rtl/
663 No longer using async rst as sync reset for the counter. lampret 8162d 11h /or1k/tags/rel_2/or1200/rtl/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8163d 08h /or1k/tags/rel_2/or1200/rtl/
636 Fixed combinational loops. lampret 8172d 16h /or1k/tags/rel_2/or1200/rtl/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8177d 11h /or1k/tags/rel_2/or1200/rtl/

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