OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_2/] [or1200/] [rtl/] - Rev 958

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7980d 13h /or1k/tags/rel_2/or1200/rtl/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7982d 13h /or1k/tags/rel_2/or1200/rtl/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7982d 13h /or1k/tags/rel_2/or1200/rtl/
942 Delayed external access at page crossing. lampret 7982d 13h /or1k/tags/rel_2/or1200/rtl/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 7994d 17h /or1k/tags/rel_2/or1200/rtl/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8010d 21h /or1k/tags/rel_2/or1200/rtl/
871 Generic flip-flop based memory macro for register file. lampret 8047d 03h /or1k/tags/rel_2/or1200/rtl/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8047d 03h /or1k/tags/rel_2/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8047d 03h /or1k/tags/rel_2/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8118d 02h /or1k/tags/rel_2/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8118d 02h /or1k/tags/rel_2/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8118d 02h /or1k/tags/rel_2/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8118d 03h /or1k/tags/rel_2/or1200/rtl/
788 Some of the warnings fixed. lampret 8118d 04h /or1k/tags/rel_2/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8119d 00h /or1k/tags/rel_2/or1200/rtl/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8119d 00h /or1k/tags/rel_2/or1200/rtl/
776 Updated defines. lampret 8119d 00h /or1k/tags/rel_2/or1200/rtl/
775 Optimized cache controller FSM. lampret 8119d 00h /or1k/tags/rel_2/or1200/rtl/
774 Removed old files. lampret 8119d 00h /or1k/tags/rel_2/or1200/rtl/
737 Added alternative for critical path in DU. lampret 8133d 18h /or1k/tags/rel_2/or1200/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.