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Rev Log message Author Age Path
203 Updated from xess branch. lampret 8363d 20h /or1k/tags/rel_21/
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf
erez 8369d 03h /or1k/tags/rel_21/
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8369d 03h /or1k/tags/rel_21/
200 Initial import simons 8372d 11h /or1k/tags/rel_21/
199 Initial import simons 8372d 12h /or1k/tags/rel_21/
198 Moved from testbench.old simons 8374d 23h /or1k/tags/rel_21/
197 This is not used any more. simons 8374d 23h /or1k/tags/rel_21/
196 Configuration SPRs added. simons 8374d 23h /or1k/tags/rel_21/
195 New test added. simons 8374d 23h /or1k/tags/rel_21/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.
chris 8375d 07h /or1k/tags/rel_21/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.
chris 8375d 08h /or1k/tags/rel_21/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.
chris 8375d 17h /or1k/tags/rel_21/
191 Added UART jitter var to sim config chris 8376d 13h /or1k/tags/rel_21/
190 Added jitter initialization chris 8376d 13h /or1k/tags/rel_21/
189 fixed mode handling for tick facility chris 8376d 13h /or1k/tags/rel_21/
188 fixed PIC interrupt controller chris 8376d 13h /or1k/tags/rel_21/
187 minor change to clear pending exception chris 8376d 13h /or1k/tags/rel_21/
186 major change to UART structure chris 8376d 13h /or1k/tags/rel_21/
185 major change to UART code chris 8376d 13h /or1k/tags/rel_21/
184 modified decode for trace debugging chris 8376d 13h /or1k/tags/rel_21/

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