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[/] [or1k/] [tags/] [rel_21/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7998d 07h /or1k/tags/rel_21/
993 Fixed IMMU bug. lampret 7998d 07h /or1k/tags/rel_21/
992 A bug when cache enabled and bus error comes fixed. simons 7998d 16h /or1k/tags/rel_21/
991 Different memory controller. simons 7998d 16h /or1k/tags/rel_21/
990 Test is now complete. simons 7998d 16h /or1k/tags/rel_21/
989 c++ is making problems so, for now, it is excluded. simons 8000d 00h /or1k/tags/rel_21/
988 ORP architecture supported. simons 8000d 15h /or1k/tags/rel_21/
987 ORP architecture supported. simons 8000d 23h /or1k/tags/rel_21/
986 outputs out of function are not registered anymore markom 8000d 23h /or1k/tags/rel_21/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8001d 11h /or1k/tags/rel_21/
984 Disable SB until it is tested lampret 8001d 11h /or1k/tags/rel_21/
983 First checkin lampret 8001d 13h /or1k/tags/rel_21/
982 Moved to sim/bin lampret 8001d 13h /or1k/tags/rel_21/
981 First checkin. lampret 8001d 13h /or1k/tags/rel_21/
980 Removed sim.tcl that shouldn't be here. lampret 8001d 13h /or1k/tags/rel_21/
979 Removed old test case binaries. lampret 8001d 13h /or1k/tags/rel_21/
978 Added variable delay for SRAM. lampret 8001d 13h /or1k/tags/rel_21/
977 Added store buffer. lampret 8001d 13h /or1k/tags/rel_21/
976 Added store buffer lampret 8001d 13h /or1k/tags/rel_21/
975 First checkin lampret 8001d 13h /or1k/tags/rel_21/

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