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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 390

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Rev Log message Author Age Path
390 Changed instantiation name of VS RAMs. lampret 8250d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8250d 21h /or1k/tags/rel_21/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8250d 21h /or1k/tags/rel_21/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8254d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8255d 08h /or1k/tags/rel_21/or1200/rtl/verilog/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8256d 03h /or1k/tags/rel_21/or1200/rtl/verilog/
360 Added OR1200_REGISTERED_INPUTS. lampret 8257d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
359 Added optional sampling of inputs. lampret 8257d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
358 Fixed virtual silicon single-port rams instantiation. lampret 8257d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
357 Fixed dbg_is_o assignment width. lampret 8257d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
356 Break point bug fixed simons 8257d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
354 Fixed width of du_except. lampret 8258d 16h /or1k/tags/rel_21/or1200/rtl/verilog/
353 Cashes disabled. simons 8259d 03h /or1k/tags/rel_21/or1200/rtl/verilog/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8260d 05h /or1k/tags/rel_21/or1200/rtl/verilog/
351 Fixed some l.trap typos. lampret 8260d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
350 For GDB changed single stepping and disabled trap exception. lampret 8260d 08h /or1k/tags/rel_21/or1200/rtl/verilog/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8265d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8265d 07h /or1k/tags/rel_21/or1200/rtl/verilog/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8266d 15h /or1k/tags/rel_21/or1200/rtl/verilog/
316 Fixed exceptions. lampret 8268d 13h /or1k/tags/rel_21/or1200/rtl/verilog/

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