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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 736

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Rev Log message Author Age Path
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8195d 00h /or1k/tags/rel_21/or1200/rtl/verilog/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8195d 00h /or1k/tags/rel_21/or1200/rtl/verilog/
668 Lapsus fixed. simons 8219d 10h /or1k/tags/rel_21/or1200/rtl/verilog/
663 No longer using async rst as sync reset for the counter. lampret 8222d 00h /or1k/tags/rel_21/or1200/rtl/verilog/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8222d 21h /or1k/tags/rel_21/or1200/rtl/verilog/
636 Fixed combinational loops. lampret 8232d 06h /or1k/tags/rel_21/or1200/rtl/verilog/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8237d 00h /or1k/tags/rel_21/or1200/rtl/verilog/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8241d 18h /or1k/tags/rel_21/or1200/rtl/verilog/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8245d 11h /or1k/tags/rel_21/or1200/rtl/verilog/
596 SR[TEE] should be zero after reset. lampret 8245d 16h /or1k/tags/rel_21/or1200/rtl/verilog/
595 Fixed 'the NPC single-step fix'. lampret 8246d 11h /or1k/tags/rel_21/or1200/rtl/verilog/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8246d 18h /or1k/tags/rel_21/or1200/rtl/verilog/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8249d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
571 Changed alignment exception EPCR. Not tested yet. lampret 8250d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
570 Fixed order of syscall and range exceptions. lampret 8250d 06h /or1k/tags/rel_21/or1200/rtl/verilog/
569 Default ASIC configuration does not sample WB inputs. lampret 8250d 16h /or1k/tags/rel_21/or1200/rtl/verilog/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8250d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8257d 01h /or1k/tags/rel_21/or1200/rtl/verilog/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8261d 04h /or1k/tags/rel_21/or1200/rtl/verilog/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8261d 17h /or1k/tags/rel_21/or1200/rtl/verilog/

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