OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 916

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8022d 12h /or1k/tags/rel_21/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8038d 16h /or1k/tags/rel_21/or1200/rtl/verilog/
871 Generic flip-flop based memory macro for register file. lampret 8074d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8074d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8074d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8145d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8145d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8145d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8145d 22h /or1k/tags/rel_21/or1200/rtl/verilog/
788 Some of the warnings fixed. lampret 8145d 23h /or1k/tags/rel_21/or1200/rtl/verilog/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8146d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8146d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
776 Updated defines. lampret 8146d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
775 Optimized cache controller FSM. lampret 8146d 19h /or1k/tags/rel_21/or1200/rtl/verilog/
774 Removed old files. lampret 8146d 20h /or1k/tags/rel_21/or1200/rtl/verilog/
737 Added alternative for critical path in DU. lampret 8161d 14h /or1k/tags/rel_21/or1200/rtl/verilog/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8164d 13h /or1k/tags/rel_21/or1200/rtl/verilog/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8164d 13h /or1k/tags/rel_21/or1200/rtl/verilog/
668 Lapsus fixed. simons 8188d 23h /or1k/tags/rel_21/or1200/rtl/verilog/
663 No longer using async rst as sync reset for the counter. lampret 8191d 13h /or1k/tags/rel_21/or1200/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.