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[/] [or1k/] [tags/] [rel_24/] - Rev 1033

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Rev Log message Author Age Path
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7995d 22h /or1k/tags/rel_24/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7996d 12h /or1k/tags/rel_24/
1031 Setting phy to 10Mbps full duplex. simons 7997d 03h /or1k/tags/rel_24/
1030 Ethernet configured for 10Mbps. simons 7998d 00h /or1k/tags/rel_24/
1029 Typing error fixed. simons 7998d 00h /or1k/tags/rel_24/
1028 Import. ivang 7998d 00h /or1k/tags/rel_24/
1027 PRINTF/printf mess fixed. simons 7998d 08h /or1k/tags/rel_24/
1026 rtems-20020807 import ivang 7998d 18h /or1k/tags/rel_24/
1025 PRINTF/printf mess fixed. simons 7998d 21h /or1k/tags/rel_24/
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 7999d 06h /or1k/tags/rel_24/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7999d 16h /or1k/tags/rel_24/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7999d 19h /or1k/tags/rel_24/
1021 *** empty log message *** rherveille 8003d 21h /or1k/tags/rel_24/
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 8003d 21h /or1k/tags/rel_24/
1019 fixed some bugs detected by Bender hardware rherveille 8003d 22h /or1k/tags/rel_24/
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8004d 04h /or1k/tags/rel_24/
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8004d 05h /or1k/tags/rel_24/
1016 64 bytes is the smallest packet size. simons 8004d 21h /or1k/tags/rel_24/
1015 Host type was not recognized. simons 8005d 07h /or1k/tags/rel_24/
1014 added _JBLEN definition for or1k ivang 8005d 20h /or1k/tags/rel_24/

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