URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [rel_24/] - Rev 360

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Rev	Log message	Author	Age	Path
360	Added OR1200_REGISTERED_INPUTS.	lampret	8300d 07h	/or1k/tags/rel_24/
359	Added optional sampling of inputs.	lampret	8300d 07h	/or1k/tags/rel_24/
358	Fixed virtual silicon single-port rams instantiation.	lampret	8300d 07h	/or1k/tags/rel_24/
357	Fixed dbg_is_o assignment width.	lampret	8300d 07h	/or1k/tags/rel_24/
356	Break point bug fixed	simons	8300d 10h	/or1k/tags/rel_24/
355	uart VAPI model improved; changes to MC and eth.	markom	8300d 17h	/or1k/tags/rel_24/
354	Fixed width of du_except.	lampret	8301d 04h	/or1k/tags/rel_24/
353	Cashes disabled.	simons	8301d 14h	/or1k/tags/rel_24/
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8302d 17h	/or1k/tags/rel_24/
351	Fixed some l.trap typos.	lampret	8302d 19h	/or1k/tags/rel_24/
350	For GDB changed single stepping and disabled trap exception.	lampret	8302d 20h	/or1k/tags/rel_24/
349	Some bugs regarding cache simulation fixed.	simons	8304d 09h	/or1k/tags/rel_24/
348	Added instructions on how to build configure.	ivang	8305d 17h	/or1k/tags/rel_24/
347	Added CRC32 calculation to Ethernet	erez	8306d 14h	/or1k/tags/rel_24/
346	Improved Ethernet simulation	erez	8306d 15h	/or1k/tags/rel_24/
345	Added check for net/ethernet.h (needed by ethernet simulator)	erez	8306d 15h	/or1k/tags/rel_24/
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8306d 17h	/or1k/tags/rel_24/
343	Small touches to test programs	erez	8306d 20h	/or1k/tags/rel_24/
342	added exception vectors to support and modified section names	markom	8307d 16h	/or1k/tags/rel_24/
341	added VAPI for uart; uart 16550 support, some bugs fixed	markom	8307d 18h	/or1k/tags/rel_24/

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[/] [or1k/] [tags/] [rel_24/] - Rev 360

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