OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24/] - Rev 991

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
991 Different memory controller. simons 8013d 18h /or1k/tags/rel_24/
990 Test is now complete. simons 8013d 18h /or1k/tags/rel_24/
989 c++ is making problems so, for now, it is excluded. simons 8015d 02h /or1k/tags/rel_24/
988 ORP architecture supported. simons 8015d 18h /or1k/tags/rel_24/
987 ORP architecture supported. simons 8016d 01h /or1k/tags/rel_24/
986 outputs out of function are not registered anymore markom 8016d 02h /or1k/tags/rel_24/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8016d 13h /or1k/tags/rel_24/
984 Disable SB until it is tested lampret 8016d 13h /or1k/tags/rel_24/
983 First checkin lampret 8016d 15h /or1k/tags/rel_24/
982 Moved to sim/bin lampret 8016d 15h /or1k/tags/rel_24/
981 First checkin. lampret 8016d 15h /or1k/tags/rel_24/
980 Removed sim.tcl that shouldn't be here. lampret 8016d 15h /or1k/tags/rel_24/
979 Removed old test case binaries. lampret 8016d 16h /or1k/tags/rel_24/
978 Added variable delay for SRAM. lampret 8016d 16h /or1k/tags/rel_24/
977 Added store buffer. lampret 8016d 16h /or1k/tags/rel_24/
976 Added store buffer lampret 8016d 16h /or1k/tags/rel_24/
975 First checkin lampret 8016d 16h /or1k/tags/rel_24/
974 Enabled what works on or1ksim and disabled other tests. lampret 8016d 18h /or1k/tags/rel_24/
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8018d 22h /or1k/tags/rel_24/
972 Interrupt suorces fixed. simons 8018d 22h /or1k/tags/rel_24/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.