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[/] [or1k/] [tags/] [rel_24/] - Rev 992

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Rev Log message Author Age Path
992 A bug when cache enabled and bus error comes fixed. simons 7990d 20h /or1k/tags/rel_24/
991 Different memory controller. simons 7990d 20h /or1k/tags/rel_24/
990 Test is now complete. simons 7990d 20h /or1k/tags/rel_24/
989 c++ is making problems so, for now, it is excluded. simons 7992d 04h /or1k/tags/rel_24/
988 ORP architecture supported. simons 7992d 19h /or1k/tags/rel_24/
987 ORP architecture supported. simons 7993d 03h /or1k/tags/rel_24/
986 outputs out of function are not registered anymore markom 7993d 03h /or1k/tags/rel_24/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7993d 15h /or1k/tags/rel_24/
984 Disable SB until it is tested lampret 7993d 15h /or1k/tags/rel_24/
983 First checkin lampret 7993d 17h /or1k/tags/rel_24/
982 Moved to sim/bin lampret 7993d 17h /or1k/tags/rel_24/
981 First checkin. lampret 7993d 17h /or1k/tags/rel_24/
980 Removed sim.tcl that shouldn't be here. lampret 7993d 17h /or1k/tags/rel_24/
979 Removed old test case binaries. lampret 7993d 17h /or1k/tags/rel_24/
978 Added variable delay for SRAM. lampret 7993d 17h /or1k/tags/rel_24/
977 Added store buffer. lampret 7993d 17h /or1k/tags/rel_24/
976 Added store buffer lampret 7993d 17h /or1k/tags/rel_24/
975 First checkin lampret 7993d 17h /or1k/tags/rel_24/
974 Enabled what works on or1ksim and disabled other tests. lampret 7993d 19h /or1k/tags/rel_24/
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7995d 23h /or1k/tags/rel_24/

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