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[/] [or1k/] [tags/] [rel_24/] [or1200/] - Rev 387

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Rev Log message Author Age Path
387 Now FPGA and ASIC target are separate. lampret 8264d 08h /or1k/tags/rel_24/or1200/
386 Fixed VS RAM instantiation - again. lampret 8264d 08h /or1k/tags/rel_24/or1200/
370 Program counter divided to PPC and NPC. simons 8268d 06h /or1k/tags/rel_24/or1200/
367 Changed DSR/DRR behavior and exception detection. lampret 8268d 19h /or1k/tags/rel_24/or1200/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8269d 14h /or1k/tags/rel_24/or1200/
360 Added OR1200_REGISTERED_INPUTS. lampret 8271d 06h /or1k/tags/rel_24/or1200/
359 Added optional sampling of inputs. lampret 8271d 06h /or1k/tags/rel_24/or1200/
358 Fixed virtual silicon single-port rams instantiation. lampret 8271d 06h /or1k/tags/rel_24/or1200/
357 Fixed dbg_is_o assignment width. lampret 8271d 06h /or1k/tags/rel_24/or1200/
356 Break point bug fixed simons 8271d 09h /or1k/tags/rel_24/or1200/
354 Fixed width of du_except. lampret 8272d 03h /or1k/tags/rel_24/or1200/
353 Cashes disabled. simons 8272d 13h /or1k/tags/rel_24/or1200/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8273d 16h /or1k/tags/rel_24/or1200/
351 Fixed some l.trap typos. lampret 8273d 18h /or1k/tags/rel_24/or1200/
350 For GDB changed single stepping and disabled trap exception. lampret 8273d 19h /or1k/tags/rel_24/or1200/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8278d 18h /or1k/tags/rel_24/or1200/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8278d 18h /or1k/tags/rel_24/or1200/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8280d 02h /or1k/tags/rel_24/or1200/
316 Fixed exceptions. lampret 8282d 00h /or1k/tags/rel_24/or1200/
271 Added missing endif lampret 8286d 13h /or1k/tags/rel_24/or1200/

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