OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24/] [or1200/] - Rev 562

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8216d 17h /or1k/tags/rel_24/or1200/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8222d 23h /or1k/tags/rel_24/or1200/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8227d 02h /or1k/tags/rel_24/or1200/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8227d 15h /or1k/tags/rel_24/or1200/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8257d 19h /or1k/tags/rel_24/or1200/
401 *** empty log message *** simons 8261d 05h /or1k/tags/rel_24/or1200/
400 force_dslot_fetch does not work - allways zero. simons 8261d 05h /or1k/tags/rel_24/or1200/
399 Trap insn couses break after exits ex_insn. simons 8261d 05h /or1k/tags/rel_24/or1200/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8264d 00h /or1k/tags/rel_24/or1200/
390 Changed instantiation name of VS RAMs. lampret 8264d 02h /or1k/tags/rel_24/or1200/
387 Now FPGA and ASIC target are separate. lampret 8264d 04h /or1k/tags/rel_24/or1200/
386 Fixed VS RAM instantiation - again. lampret 8264d 04h /or1k/tags/rel_24/or1200/
370 Program counter divided to PPC and NPC. simons 8268d 02h /or1k/tags/rel_24/or1200/
367 Changed DSR/DRR behavior and exception detection. lampret 8268d 15h /or1k/tags/rel_24/or1200/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8269d 10h /or1k/tags/rel_24/or1200/
360 Added OR1200_REGISTERED_INPUTS. lampret 8271d 02h /or1k/tags/rel_24/or1200/
359 Added optional sampling of inputs. lampret 8271d 02h /or1k/tags/rel_24/or1200/
358 Fixed virtual silicon single-port rams instantiation. lampret 8271d 02h /or1k/tags/rel_24/or1200/
357 Fixed dbg_is_o assignment width. lampret 8271d 02h /or1k/tags/rel_24/or1200/
356 Break point bug fixed simons 8271d 05h /or1k/tags/rel_24/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.