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[/] [or1k/] [tags/] [rel_25/] - Rev 363

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Rev Log message Author Age Path
363 program can be stepped and continued before running it, supporting low level debugging markom 8300d 12h /or1k/tags/rel_25/
362 some changes based on current modifications to or1k; cleaner register naming; ctrl-c causes stepi; write&read pc work on next instruction markom 8300d 17h /or1k/tags/rel_25/
361 set config command added; config struct has been divided into two structs - config and runtime; -f option allows multiple config scripts markom 8300d 18h /or1k/tags/rel_25/
360 Added OR1200_REGISTERED_INPUTS. lampret 8301d 05h /or1k/tags/rel_25/
359 Added optional sampling of inputs. lampret 8301d 05h /or1k/tags/rel_25/
358 Fixed virtual silicon single-port rams instantiation. lampret 8301d 05h /or1k/tags/rel_25/
357 Fixed dbg_is_o assignment width. lampret 8301d 05h /or1k/tags/rel_25/
356 Break point bug fixed simons 8301d 08h /or1k/tags/rel_25/
355 uart VAPI model improved; changes to MC and eth. markom 8301d 15h /or1k/tags/rel_25/
354 Fixed width of du_except. lampret 8302d 01h /or1k/tags/rel_25/
353 Cashes disabled. simons 8302d 12h /or1k/tags/rel_25/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8303d 15h /or1k/tags/rel_25/
351 Fixed some l.trap typos. lampret 8303d 16h /or1k/tags/rel_25/
350 For GDB changed single stepping and disabled trap exception. lampret 8303d 18h /or1k/tags/rel_25/
349 Some bugs regarding cache simulation fixed. simons 8305d 06h /or1k/tags/rel_25/
348 Added instructions on how to build configure. ivang 8306d 14h /or1k/tags/rel_25/
347 Added CRC32 calculation to Ethernet erez 8307d 11h /or1k/tags/rel_25/
346 Improved Ethernet simulation erez 8307d 13h /or1k/tags/rel_25/
345 Added check for net/ethernet.h (needed by ethernet simulator) erez 8307d 13h /or1k/tags/rel_25/
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8307d 15h /or1k/tags/rel_25/

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