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[/] [or1k/] [tags/] [rel_25/] - Rev 642

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Rev	Log message	Author	Age	Path
642	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8270d 08h	/or1k/tags/rel_25/
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8270d 08h	/or1k/tags/rel_25/
640	Merge profiler and mprofiler with sim.	ivang	8270d 09h	/or1k/tags/rel_25/
639	MMU cache inhibit bit test added.	simons	8273d 00h	/or1k/tags/rel_25/
638	TLBTR CI bit is now working properly.	simons	8273d 00h	/or1k/tags/rel_25/
637	Updated file names.	lampret	8273d 01h	/or1k/tags/rel_25/
636	Fixed combinational loops.	lampret	8273d 01h	/or1k/tags/rel_25/
635	Fixed Makefile bug.	ivang	8273d 03h	/or1k/tags/rel_25/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8274d 04h	/or1k/tags/rel_25/
633	Bug fix in command line parser.	ivang	8274d 05h	/or1k/tags/rel_25/
632	profiler and mprofiler merged into sim.	ivang	8275d 00h	/or1k/tags/rel_25/
631	Real cache access is simulated now.	simons	8275d 23h	/or1k/tags/rel_25/
630	some bug fixes in store buffer analysis	markom	8276d 08h	/or1k/tags/rel_25/
629	typo fixed	markom	8276d 11h	/or1k/tags/rel_25/
627	or32 restored	markom	8276d 12h	/or1k/tags/rel_25/
626	store buffer added	markom	8276d 12h	/or1k/tags/rel_25/
625	Bus error bug fixed. Cache routines added.	simons	8277d 04h	/or1k/tags/rel_25/
624	Added logging of writes/read to/from SPR registers.	ivang	8277d 05h	/or1k/tags/rel_25/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8277d 07h	/or1k/tags/rel_25/
622	Cache test works on hardware.	simons	8277d 10h	/or1k/tags/rel_25/

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[/] [or1k/] [tags/] [rel_25/] - Rev 642

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