OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25/] - Rev 655

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
655 TLB registers addresses changed. simons 8257d 00h /or1k/tags/rel_25/
654 This is repaired in new versions of uClinux. simons 8257d 00h /or1k/tags/rel_25/
653 Some cleanup. simons 8257d 00h /or1k/tags/rel_25/
652 Some cleanup. simons 8257d 01h /or1k/tags/rel_25/
651 Some cleanup. simons 8257d 01h /or1k/tags/rel_25/
650 Some cleanup. simons 8257d 02h /or1k/tags/rel_25/
649 Some cleanup. simons 8257d 02h /or1k/tags/rel_25/
648 fb now works in system memory markom 8258d 11h /or1k/tags/rel_25/
647 some changes to fb to make it compatible with HW markom 8259d 06h /or1k/tags/rel_25/
646 some bugs fixed markom 8259d 08h /or1k/tags/rel_25/
645 simple frame buffer peripheral with test added markom 8259d 11h /or1k/tags/rel_25/
644 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8260d 06h /or1k/tags/rel_25/
643 Quick bug fix. ivang 8260d 07h /or1k/tags/rel_25/
642 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8260d 07h /or1k/tags/rel_25/
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8260d 07h /or1k/tags/rel_25/
640 Merge profiler and mprofiler with sim. ivang 8260d 08h /or1k/tags/rel_25/
639 MMU cache inhibit bit test added. simons 8262d 23h /or1k/tags/rel_25/
638 TLBTR CI bit is now working properly. simons 8262d 23h /or1k/tags/rel_25/
637 Updated file names. lampret 8263d 00h /or1k/tags/rel_25/
636 Fixed combinational loops. lampret 8263d 00h /or1k/tags/rel_25/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.