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[/] [or1k/] [tags/] [rel_25/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8010d 20h /or1k/tags/rel_25/
993 Fixed IMMU bug. lampret 8010d 20h /or1k/tags/rel_25/
992 A bug when cache enabled and bus error comes fixed. simons 8011d 05h /or1k/tags/rel_25/
991 Different memory controller. simons 8011d 05h /or1k/tags/rel_25/
990 Test is now complete. simons 8011d 05h /or1k/tags/rel_25/
989 c++ is making problems so, for now, it is excluded. simons 8012d 13h /or1k/tags/rel_25/
988 ORP architecture supported. simons 8013d 05h /or1k/tags/rel_25/
987 ORP architecture supported. simons 8013d 12h /or1k/tags/rel_25/
986 outputs out of function are not registered anymore markom 8013d 13h /or1k/tags/rel_25/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8014d 00h /or1k/tags/rel_25/
984 Disable SB until it is tested lampret 8014d 00h /or1k/tags/rel_25/
983 First checkin lampret 8014d 02h /or1k/tags/rel_25/
982 Moved to sim/bin lampret 8014d 02h /or1k/tags/rel_25/
981 First checkin. lampret 8014d 02h /or1k/tags/rel_25/
980 Removed sim.tcl that shouldn't be here. lampret 8014d 02h /or1k/tags/rel_25/
979 Removed old test case binaries. lampret 8014d 02h /or1k/tags/rel_25/
978 Added variable delay for SRAM. lampret 8014d 02h /or1k/tags/rel_25/
977 Added store buffer. lampret 8014d 02h /or1k/tags/rel_25/
976 Added store buffer lampret 8014d 03h /or1k/tags/rel_25/
975 First checkin lampret 8014d 03h /or1k/tags/rel_25/

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