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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog/] - Rev 1022

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Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7975d 14h /or1k/tags/rel_25/or1200/rtl/verilog/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7982d 11h /or1k/tags/rel_25/or1200/rtl/verilog/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7988d 11h /or1k/tags/rel_25/or1200/rtl/verilog/
993 Fixed IMMU bug. lampret 7988d 11h /or1k/tags/rel_25/or1200/rtl/verilog/
984 Disable SB until it is tested lampret 7991d 15h /or1k/tags/rel_25/or1200/rtl/verilog/
977 Added store buffer. lampret 7991d 17h /or1k/tags/rel_25/or1200/rtl/verilog/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7995d 07h /or1k/tags/rel_25/or1200/rtl/verilog/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7996d 06h /or1k/tags/rel_25/or1200/rtl/verilog/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7998d 07h /or1k/tags/rel_25/or1200/rtl/verilog/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 7998d 07h /or1k/tags/rel_25/or1200/rtl/verilog/
942 Delayed external access at page crossing. lampret 7998d 07h /or1k/tags/rel_25/or1200/rtl/verilog/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8010d 11h /or1k/tags/rel_25/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8026d 15h /or1k/tags/rel_25/or1200/rtl/verilog/
871 Generic flip-flop based memory macro for register file. lampret 8062d 20h /or1k/tags/rel_25/or1200/rtl/verilog/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8062d 21h /or1k/tags/rel_25/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8062d 21h /or1k/tags/rel_25/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8133d 20h /or1k/tags/rel_25/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8133d 20h /or1k/tags/rel_25/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8133d 20h /or1k/tags/rel_25/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8133d 20h /or1k/tags/rel_25/or1200/rtl/verilog/

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