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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] - Rev 1131

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Rev Log message Author Age Path
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7765d 19h /or1k/tags/rel_26/or1200/rtl/
1130 RFRAM type always need to be defined. lampret 7765d 19h /or1k/tags/rel_26/or1200/rtl/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7765d 19h /or1k/tags/rel_26/or1200/rtl/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7840d 17h /or1k/tags/rel_26/or1200/rtl/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7885d 12h /or1k/tags/rel_26/or1200/rtl/
1083 SB mem width fixed. simons 7917d 07h /or1k/tags/rel_26/or1200/rtl/
1079 RAMs wrong connected to the BIST scan chain. mohor 7926d 04h /or1k/tags/rel_26/or1200/rtl/
1078 Previous check-in was done by mistake. mohor 7926d 06h /or1k/tags/rel_26/or1200/rtl/
1077 Signal scanb_sen renamed to scanb_en. mohor 7926d 06h /or1k/tags/rel_26/or1200/rtl/
1069 Signal scanb_eni renamed to scanb_en mohor 7929d 22h /or1k/tags/rel_26/or1200/rtl/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7937d 01h /or1k/tags/rel_26/or1200/rtl/
1055 Removed obsolete comment. lampret 7968d 17h /or1k/tags/rel_26/or1200/rtl/
1054 Fixed a combinational loop. lampret 7968d 18h /or1k/tags/rel_26/or1200/rtl/
1053 Disabled cache inhibit atttribute. lampret 7968d 18h /or1k/tags/rel_26/or1200/rtl/
1038 Fixed a typo, reported by Taylor Su. lampret 7976d 01h /or1k/tags/rel_26/or1200/rtl/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7976d 15h /or1k/tags/rel_26/or1200/rtl/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7977d 01h /or1k/tags/rel_26/or1200/rtl/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7977d 15h /or1k/tags/rel_26/or1200/rtl/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7980d 20h /or1k/tags/rel_26/or1200/rtl/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7980d 22h /or1k/tags/rel_26/or1200/rtl/

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