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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] - Rev 1155

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Rev Log message Author Age Path
1155 No functional change. Only added customization for exception vectors. lampret 7810d 09h /or1k/tags/rel_26/or1200/rtl/verilog/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7823d 11h /or1k/tags/rel_26/or1200/rtl/verilog/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7823d 11h /or1k/tags/rel_26/or1200/rtl/verilog/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7824d 06h /or1k/tags/rel_26/or1200/rtl/verilog/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7824d 06h /or1k/tags/rel_26/or1200/rtl/verilog/
1130 RFRAM type always need to be defined. lampret 7824d 07h /or1k/tags/rel_26/or1200/rtl/verilog/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7824d 07h /or1k/tags/rel_26/or1200/rtl/verilog/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7899d 04h /or1k/tags/rel_26/or1200/rtl/verilog/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7943d 23h /or1k/tags/rel_26/or1200/rtl/verilog/
1083 SB mem width fixed. simons 7975d 18h /or1k/tags/rel_26/or1200/rtl/verilog/
1079 RAMs wrong connected to the BIST scan chain. mohor 7984d 15h /or1k/tags/rel_26/or1200/rtl/verilog/
1078 Previous check-in was done by mistake. mohor 7984d 17h /or1k/tags/rel_26/or1200/rtl/verilog/
1077 Signal scanb_sen renamed to scanb_en. mohor 7984d 17h /or1k/tags/rel_26/or1200/rtl/verilog/
1069 Signal scanb_eni renamed to scanb_en mohor 7988d 10h /or1k/tags/rel_26/or1200/rtl/verilog/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7995d 12h /or1k/tags/rel_26/or1200/rtl/verilog/
1055 Removed obsolete comment. lampret 8027d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
1054 Fixed a combinational loop. lampret 8027d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
1053 Disabled cache inhibit atttribute. lampret 8027d 05h /or1k/tags/rel_26/or1200/rtl/verilog/
1038 Fixed a typo, reported by Taylor Su. lampret 8034d 12h /or1k/tags/rel_26/or1200/rtl/verilog/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8035d 02h /or1k/tags/rel_26/or1200/rtl/verilog/

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