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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] - Rev 610

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Rev Log message Author Age Path
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8226d 13h /or1k/tags/rel_26/or1200/rtl/verilog/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8230d 07h /or1k/tags/rel_26/or1200/rtl/verilog/
596 SR[TEE] should be zero after reset. lampret 8230d 12h /or1k/tags/rel_26/or1200/rtl/verilog/
595 Fixed 'the NPC single-step fix'. lampret 8231d 07h /or1k/tags/rel_26/or1200/rtl/verilog/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8231d 13h /or1k/tags/rel_26/or1200/rtl/verilog/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8234d 15h /or1k/tags/rel_26/or1200/rtl/verilog/
571 Changed alignment exception EPCR. Not tested yet. lampret 8235d 00h /or1k/tags/rel_26/or1200/rtl/verilog/
570 Fixed order of syscall and range exceptions. lampret 8235d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
569 Default ASIC configuration does not sample WB inputs. lampret 8235d 12h /or1k/tags/rel_26/or1200/rtl/verilog/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8235d 15h /or1k/tags/rel_26/or1200/rtl/verilog/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8241d 21h /or1k/tags/rel_26/or1200/rtl/verilog/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8246d 00h /or1k/tags/rel_26/or1200/rtl/verilog/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8246d 13h /or1k/tags/rel_26/or1200/rtl/verilog/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8276d 16h /or1k/tags/rel_26/or1200/rtl/verilog/
401 *** empty log message *** simons 8280d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8280d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8280d 02h /or1k/tags/rel_26/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8282d 22h /or1k/tags/rel_26/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8283d 00h /or1k/tags/rel_26/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8283d 02h /or1k/tags/rel_26/or1200/rtl/verilog/

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