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[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 962

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Rev	Log message	Author	Age	Path
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	7999d 07h	/or1k/tags/rel_27/or1200/rtl/
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8000d 06h	/or1k/tags/rel_27/or1200/rtl/
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8002d 07h	/or1k/tags/rel_27/or1200/rtl/
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8002d 07h	/or1k/tags/rel_27/or1200/rtl/
942	Delayed external access at page crossing.	lampret	8002d 07h	/or1k/tags/rel_27/or1200/rtl/
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8014d 11h	/or1k/tags/rel_27/or1200/rtl/
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8030d 15h	/or1k/tags/rel_27/or1200/rtl/
871	Generic flip-flop based memory macro for register file.	lampret	8066d 20h	/or1k/tags/rel_27/or1200/rtl/
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8066d 21h	/or1k/tags/rel_27/or1200/rtl/
869	Added generic flip-flop based memory macro instantiation.	lampret	8066d 21h	/or1k/tags/rel_27/or1200/rtl/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8137d 20h	/or1k/tags/rel_27/or1200/rtl/
794	Added again just recently removed full_case directive	lampret	8137d 20h	/or1k/tags/rel_27/or1200/rtl/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8137d 20h	/or1k/tags/rel_27/or1200/rtl/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8137d 20h	/or1k/tags/rel_27/or1200/rtl/
788	Some of the warnings fixed.	lampret	8137d 22h	/or1k/tags/rel_27/or1200/rtl/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8138d 17h	/or1k/tags/rel_27/or1200/rtl/
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8138d 18h	/or1k/tags/rel_27/or1200/rtl/
776	Updated defines.	lampret	8138d 18h	/or1k/tags/rel_27/or1200/rtl/
775	Optimized cache controller FSM.	lampret	8138d 18h	/or1k/tags/rel_27/or1200/rtl/
774	Removed old files.	lampret	8138d 18h	/or1k/tags/rel_27/or1200/rtl/

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[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 962

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