OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_27/] [or1200/] [rtl/] - Rev 994

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8016d 20h /or1k/tags/rel_27/or1200/rtl/
993 Fixed IMMU bug. lampret 8016d 20h /or1k/tags/rel_27/or1200/rtl/
984 Disable SB until it is tested lampret 8020d 01h /or1k/tags/rel_27/or1200/rtl/
977 Added store buffer. lampret 8020d 03h /or1k/tags/rel_27/or1200/rtl/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8023d 17h /or1k/tags/rel_27/or1200/rtl/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8024d 16h /or1k/tags/rel_27/or1200/rtl/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8026d 17h /or1k/tags/rel_27/or1200/rtl/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8026d 17h /or1k/tags/rel_27/or1200/rtl/
942 Delayed external access at page crossing. lampret 8026d 17h /or1k/tags/rel_27/or1200/rtl/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8038d 21h /or1k/tags/rel_27/or1200/rtl/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8055d 00h /or1k/tags/rel_27/or1200/rtl/
871 Generic flip-flop based memory macro for register file. lampret 8091d 06h /or1k/tags/rel_27/or1200/rtl/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8091d 06h /or1k/tags/rel_27/or1200/rtl/
869 Added generic flip-flop based memory macro instantiation. lampret 8091d 06h /or1k/tags/rel_27/or1200/rtl/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8162d 06h /or1k/tags/rel_27/or1200/rtl/
794 Added again just recently removed full_case directive lampret 8162d 06h /or1k/tags/rel_27/or1200/rtl/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8162d 06h /or1k/tags/rel_27/or1200/rtl/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8162d 06h /or1k/tags/rel_27/or1200/rtl/
788 Some of the warnings fixed. lampret 8162d 07h /or1k/tags/rel_27/or1200/rtl/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8163d 03h /or1k/tags/rel_27/or1200/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.