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[/] [or1k/] [tags/] [rel_28/] [or1200/] [rtl/] [verilog/] - Rev 1186

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Rev Log message Author Age Path
1186 Added support for rams with byte write access. simons 7652d 08h /or1k/tags/rel_28/or1200/rtl/verilog/
1184 Scan signals mess fixed. simons 7659d 01h /or1k/tags/rel_28/or1200/rtl/verilog/
1179 BIST interface added for Artisan memory instances. simons 7667d 04h /or1k/tags/rel_28/or1200/rtl/verilog/
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7733d 15h /or1k/tags/rel_28/or1200/rtl/verilog/
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7776d 17h /or1k/tags/rel_28/or1200/rtl/verilog/
1155 No functional change. Only added customization for exception vectors. lampret 7779d 19h /or1k/tags/rel_28/or1200/rtl/verilog/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7792d 21h /or1k/tags/rel_28/or1200/rtl/verilog/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7792d 21h /or1k/tags/rel_28/or1200/rtl/verilog/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7793d 16h /or1k/tags/rel_28/or1200/rtl/verilog/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7793d 16h /or1k/tags/rel_28/or1200/rtl/verilog/
1130 RFRAM type always need to be defined. lampret 7793d 16h /or1k/tags/rel_28/or1200/rtl/verilog/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7793d 16h /or1k/tags/rel_28/or1200/rtl/verilog/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7868d 14h /or1k/tags/rel_28/or1200/rtl/verilog/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7913d 09h /or1k/tags/rel_28/or1200/rtl/verilog/
1083 SB mem width fixed. simons 7945d 04h /or1k/tags/rel_28/or1200/rtl/verilog/
1079 RAMs wrong connected to the BIST scan chain. mohor 7954d 01h /or1k/tags/rel_28/or1200/rtl/verilog/
1078 Previous check-in was done by mistake. mohor 7954d 02h /or1k/tags/rel_28/or1200/rtl/verilog/
1077 Signal scanb_sen renamed to scanb_en. mohor 7954d 03h /or1k/tags/rel_28/or1200/rtl/verilog/
1069 Signal scanb_eni renamed to scanb_en mohor 7957d 19h /or1k/tags/rel_28/or1200/rtl/verilog/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7964d 22h /or1k/tags/rel_28/or1200/rtl/verilog/

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