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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] - Rev 402

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Rev Log message Author Age Path
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8253d 18h /or1k/tags/rel_29/or1200/rtl/verilog/
401 *** empty log message *** simons 8257d 04h /or1k/tags/rel_29/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8257d 04h /or1k/tags/rel_29/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8257d 04h /or1k/tags/rel_29/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8260d 00h /or1k/tags/rel_29/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8260d 02h /or1k/tags/rel_29/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8260d 03h /or1k/tags/rel_29/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8260d 03h /or1k/tags/rel_29/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8264d 01h /or1k/tags/rel_29/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8264d 14h /or1k/tags/rel_29/or1200/rtl/verilog/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8265d 09h /or1k/tags/rel_29/or1200/rtl/verilog/
360 Added OR1200_REGISTERED_INPUTS. lampret 8267d 01h /or1k/tags/rel_29/or1200/rtl/verilog/
359 Added optional sampling of inputs. lampret 8267d 01h /or1k/tags/rel_29/or1200/rtl/verilog/
358 Fixed virtual silicon single-port rams instantiation. lampret 8267d 01h /or1k/tags/rel_29/or1200/rtl/verilog/
357 Fixed dbg_is_o assignment width. lampret 8267d 01h /or1k/tags/rel_29/or1200/rtl/verilog/
356 Break point bug fixed simons 8267d 04h /or1k/tags/rel_29/or1200/rtl/verilog/
354 Fixed width of du_except. lampret 8267d 22h /or1k/tags/rel_29/or1200/rtl/verilog/
353 Cashes disabled. simons 8268d 08h /or1k/tags/rel_29/or1200/rtl/verilog/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8269d 11h /or1k/tags/rel_29/or1200/rtl/verilog/
351 Fixed some l.trap typos. lampret 8269d 13h /or1k/tags/rel_29/or1200/rtl/verilog/

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