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[/] [or1k/] [tags/] [rel_3/] [or1200/] [rtl/] [verilog/] - Rev 328

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Rev Log message Author Age Path
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8285d 18h /or1k/tags/rel_3/or1200/rtl/verilog/
316 Fixed exceptions. lampret 8287d 16h /or1k/tags/rel_3/or1200/rtl/verilog/
271 Added missing endif lampret 8292d 05h /or1k/tags/rel_3/or1200/rtl/verilog/
265 Modified virtual silicon instantiations. lampret 8295d 01h /or1k/tags/rel_3/or1200/rtl/verilog/
220 Fixed parameters in generic sprams. lampret 8306d 00h /or1k/tags/rel_3/or1200/rtl/verilog/
219 Fixed sensitivity list. lampret 8307d 02h /or1k/tags/rel_3/or1200/rtl/verilog/
218 Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. lampret 8307d 02h /or1k/tags/rel_3/or1200/rtl/verilog/
217 Fixed some synthesis warnings. Configured with caches and MMUs. lampret 8308d 21h /or1k/tags/rel_3/or1200/rtl/verilog/
216 No longer needed. lampret 8314d 07h /or1k/tags/rel_3/or1200/rtl/verilog/
215 MP3 version. lampret 8314d 07h /or1k/tags/rel_3/or1200/rtl/verilog/
210 Updated debug. More cleanup. Added MAC. lampret 8327d 16h /or1k/tags/rel_3/or1200/rtl/verilog/
209 Update debug. lampret 8329d 20h /or1k/tags/rel_3/or1200/rtl/verilog/
205 Adding debug capabilities. Half done. lampret 8335d 15h /or1k/tags/rel_3/or1200/rtl/verilog/
203 Updated from xess branch. lampret 8339d 20h /or1k/tags/rel_3/or1200/rtl/verilog/
176 IC enable/disable. lampret 8372d 12h /or1k/tags/rel_3/or1200/rtl/verilog/
172 Removing obsolete files. lampret 8376d 16h /or1k/tags/rel_3/or1200/rtl/verilog/
170 Added cfg regs. Moved all defines into one defines.v file. More cleanup. lampret 8376d 16h /or1k/tags/rel_3/or1200/rtl/verilog/
168 Major clean-up. lampret 8380d 06h /or1k/tags/rel_3/or1200/rtl/verilog/
166 Fixed RAM's oen bug. Cache bypass under development. lampret 8398d 17h /or1k/tags/rel_3/or1200/rtl/verilog/
163 Forgot files.f file. lampret 8400d 19h /or1k/tags/rel_3/or1200/rtl/verilog/

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