OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_3/] [or1200/] [rtl/] [verilog/] - Rev 356

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
356 Break point bug fixed simons 8258d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
354 Fixed width of du_except. lampret 8259d 13h /or1k/tags/rel_3/or1200/rtl/verilog/
353 Cashes disabled. simons 8259d 23h /or1k/tags/rel_3/or1200/rtl/verilog/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8261d 02h /or1k/tags/rel_3/or1200/rtl/verilog/
351 Fixed some l.trap typos. lampret 8261d 04h /or1k/tags/rel_3/or1200/rtl/verilog/
350 For GDB changed single stepping and disabled trap exception. lampret 8261d 05h /or1k/tags/rel_3/or1200/rtl/verilog/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8266d 04h /or1k/tags/rel_3/or1200/rtl/verilog/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8266d 04h /or1k/tags/rel_3/or1200/rtl/verilog/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8267d 12h /or1k/tags/rel_3/or1200/rtl/verilog/
316 Fixed exceptions. lampret 8269d 10h /or1k/tags/rel_3/or1200/rtl/verilog/
271 Added missing endif lampret 8273d 23h /or1k/tags/rel_3/or1200/rtl/verilog/
265 Modified virtual silicon instantiations. lampret 8276d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
220 Fixed parameters in generic sprams. lampret 8287d 18h /or1k/tags/rel_3/or1200/rtl/verilog/
219 Fixed sensitivity list. lampret 8288d 20h /or1k/tags/rel_3/or1200/rtl/verilog/
218 Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. lampret 8288d 20h /or1k/tags/rel_3/or1200/rtl/verilog/
217 Fixed some synthesis warnings. Configured with caches and MMUs. lampret 8290d 14h /or1k/tags/rel_3/or1200/rtl/verilog/
216 No longer needed. lampret 8296d 00h /or1k/tags/rel_3/or1200/rtl/verilog/
215 MP3 version. lampret 8296d 01h /or1k/tags/rel_3/or1200/rtl/verilog/
210 Updated debug. More cleanup. Added MAC. lampret 8309d 09h /or1k/tags/rel_3/or1200/rtl/verilog/
209 Update debug. lampret 8311d 14h /or1k/tags/rel_3/or1200/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.