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[/] [or1k/] [tags/] [rel_3/] [or1200/] [rtl/] [verilog/] - Rev 870

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870 Added defines for enabling generic FF based memory macro for register file. lampret 8057d 22h /or1k/tags/rel_3/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8057d 22h /or1k/tags/rel_3/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8128d 21h /or1k/tags/rel_3/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8128d 21h /or1k/tags/rel_3/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8128d 22h /or1k/tags/rel_3/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8128d 22h /or1k/tags/rel_3/or1200/rtl/verilog/
788 Some of the warnings fixed. lampret 8128d 23h /or1k/tags/rel_3/or1200/rtl/verilog/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8129d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8129d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
776 Updated defines. lampret 8129d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
775 Optimized cache controller FSM. lampret 8129d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
774 Removed old files. lampret 8129d 19h /or1k/tags/rel_3/or1200/rtl/verilog/
737 Added alternative for critical path in DU. lampret 8144d 13h /or1k/tags/rel_3/or1200/rtl/verilog/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8147d 13h /or1k/tags/rel_3/or1200/rtl/verilog/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8147d 13h /or1k/tags/rel_3/or1200/rtl/verilog/
668 Lapsus fixed. simons 8171d 22h /or1k/tags/rel_3/or1200/rtl/verilog/
663 No longer using async rst as sync reset for the counter. lampret 8174d 12h /or1k/tags/rel_3/or1200/rtl/verilog/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8175d 09h /or1k/tags/rel_3/or1200/rtl/verilog/
636 Fixed combinational loops. lampret 8184d 18h /or1k/tags/rel_3/or1200/rtl/verilog/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8189d 13h /or1k/tags/rel_3/or1200/rtl/verilog/

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