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[/] [or1k/] [tags/] [rel_4/] [or1200/] [rtl/] - Rev 610

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Rev	Log message	Author	Age	Path
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8233d 01h	/or1k/tags/rel_4/or1200/rtl/
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8236d 19h	/or1k/tags/rel_4/or1200/rtl/
596	SR[TEE] should be zero after reset.	lampret	8237d 00h	/or1k/tags/rel_4/or1200/rtl/
595	Fixed 'the NPC single-step fix'.	lampret	8237d 19h	/or1k/tags/rel_4/or1200/rtl/
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8238d 01h	/or1k/tags/rel_4/or1200/rtl/
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8241d 03h	/or1k/tags/rel_4/or1200/rtl/
571	Changed alignment exception EPCR. Not tested yet.	lampret	8241d 12h	/or1k/tags/rel_4/or1200/rtl/
570	Fixed order of syscall and range exceptions.	lampret	8241d 14h	/or1k/tags/rel_4/or1200/rtl/
569	Default ASIC configuration does not sample WB inputs.	lampret	8241d 23h	/or1k/tags/rel_4/or1200/rtl/
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8242d 03h	/or1k/tags/rel_4/or1200/rtl/
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8248d 08h	/or1k/tags/rel_4/or1200/rtl/
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8252d 12h	/or1k/tags/rel_4/or1200/rtl/
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8253d 01h	/or1k/tags/rel_4/or1200/rtl/
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8283d 04h	/or1k/tags/rel_4/or1200/rtl/
401	* empty log message *	simons	8286d 14h	/or1k/tags/rel_4/or1200/rtl/
400	force_dslot_fetch does not work - allways zero.	simons	8286d 14h	/or1k/tags/rel_4/or1200/rtl/
399	Trap insn couses break after exits ex_insn.	simons	8286d 14h	/or1k/tags/rel_4/or1200/rtl/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8289d 10h	/or1k/tags/rel_4/or1200/rtl/
390	Changed instantiation name of VS RAMs.	lampret	8289d 12h	/or1k/tags/rel_4/or1200/rtl/
387	Now FPGA and ASIC target are separate.	lampret	8289d 13h	/or1k/tags/rel_4/or1200/rtl/

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[/] [or1k/] [tags/] [rel_4/] [or1200/] [rtl/] - Rev 610

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