URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_5/] - Rev 646

Rev	Log message	Author	Age	Path
646	some bugs fixed	markom	8203d 20h	/or1k/tags/rel_5/
645	simple frame buffer peripheral with test added	markom	8204d 00h	/or1k/tags/rel_5/
644	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8204d 19h	/or1k/tags/rel_5/
643	Quick bug fix.	ivang	8204d 19h	/or1k/tags/rel_5/
642	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8204d 19h	/or1k/tags/rel_5/
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8204d 19h	/or1k/tags/rel_5/
640	Merge profiler and mprofiler with sim.	ivang	8204d 21h	/or1k/tags/rel_5/
639	MMU cache inhibit bit test added.	simons	8207d 11h	/or1k/tags/rel_5/
638	TLBTR CI bit is now working properly.	simons	8207d 12h	/or1k/tags/rel_5/
637	Updated file names.	lampret	8207d 13h	/or1k/tags/rel_5/
636	Fixed combinational loops.	lampret	8207d 13h	/or1k/tags/rel_5/
635	Fixed Makefile bug.	ivang	8207d 15h	/or1k/tags/rel_5/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8208d 16h	/or1k/tags/rel_5/
633	Bug fix in command line parser.	ivang	8208d 17h	/or1k/tags/rel_5/
632	profiler and mprofiler merged into sim.	ivang	8209d 12h	/or1k/tags/rel_5/
631	Real cache access is simulated now.	simons	8210d 11h	/or1k/tags/rel_5/
630	some bug fixes in store buffer analysis	markom	8210d 20h	/or1k/tags/rel_5/
629	typo fixed	markom	8210d 23h	/or1k/tags/rel_5/
627	or32 restored	markom	8211d 00h	/or1k/tags/rel_5/
626	store buffer added	markom	8211d 00h	/or1k/tags/rel_5/