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[/] [or1k/] [tags/] [rel_5/] - Rev 895

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Rev	Log message	Author	Age	Path
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8018d 02h	/or1k/tags/rel_5/
894	Typing mistake fixed.	simons	8020d 00h	/or1k/tags/rel_5/
893	Ethernet tested on xess board.	simons	8020d 00h	/or1k/tags/rel_5/
891	eth_ledc not positioned correctly. Fixed.	mohor	8020d 01h	/or1k/tags/rel_5/
890	Ethernet RXD pins were not positioned correctly.	mohor	8020d 01h	/or1k/tags/rel_5/
889	Modified Ethernet model.	ivang	8020d 06h	/or1k/tags/rel_5/
888	LCD 320x240 configuration added.	simons	8020d 23h	/or1k/tags/rel_5/
887	Some additional instructions fixes.	simons	8021d 09h	/or1k/tags/rel_5/
886	MMU registers reserved fields protected from writing.	simons	8022d 08h	/or1k/tags/rel_5/
885	Some incorrect instructions fixed.	simons	8022d 11h	/or1k/tags/rel_5/
884	code cleaning - a lot of global variables moved to runtime struct	markom	8022d 14h	/or1k/tags/rel_5/
883	cuc updated, cuc prompt parsing; CSM analysis	markom	8023d 09h	/or1k/tags/rel_5/
882	Routine for adjusting read and write delay for devices added.	simons	8025d 12h	/or1k/tags/rel_5/
881	Normally uart rx and tx files should be in the current folder.	mohor	8026d 05h	/or1k/tags/rel_5/
880	Library should not be erased during clean.	mohor	8026d 06h	/or1k/tags/rel_5/
879	Initial version of OpenRISC Custom Unit Compiler added	markom	8028d 08h	/or1k/tags/rel_5/
878	first release of atabug	rherveille	8030d 02h	/or1k/tags/rel_5/
877	ata beta release	rherveille	8030d 02h	/or1k/tags/rel_5/
876	Beta release of ATA simulation	rherveille	8030d 02h	/or1k/tags/rel_5/
875	libgcc is moved here to avoid the mess with the folders.	simons	8030d 14h	/or1k/tags/rel_5/

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[/] [or1k/] [tags/] [rel_5/] - Rev 895

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