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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 367

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Rev Log message Author Age Path
367 Changed DSR/DRR behavior and exception detection. lampret 8302d 03h /or1k/tags/rel_5/or1200/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8302d 21h /or1k/tags/rel_5/or1200/
360 Added OR1200_REGISTERED_INPUTS. lampret 8304d 14h /or1k/tags/rel_5/or1200/
359 Added optional sampling of inputs. lampret 8304d 14h /or1k/tags/rel_5/or1200/
358 Fixed virtual silicon single-port rams instantiation. lampret 8304d 14h /or1k/tags/rel_5/or1200/
357 Fixed dbg_is_o assignment width. lampret 8304d 14h /or1k/tags/rel_5/or1200/
356 Break point bug fixed simons 8304d 16h /or1k/tags/rel_5/or1200/
354 Fixed width of du_except. lampret 8305d 10h /or1k/tags/rel_5/or1200/
353 Cashes disabled. simons 8305d 21h /or1k/tags/rel_5/or1200/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8307d 00h /or1k/tags/rel_5/or1200/
351 Fixed some l.trap typos. lampret 8307d 01h /or1k/tags/rel_5/or1200/
350 For GDB changed single stepping and disabled trap exception. lampret 8307d 03h /or1k/tags/rel_5/or1200/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8312d 01h /or1k/tags/rel_5/or1200/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8312d 01h /or1k/tags/rel_5/or1200/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8313d 09h /or1k/tags/rel_5/or1200/
316 Fixed exceptions. lampret 8315d 07h /or1k/tags/rel_5/or1200/
271 Added missing endif lampret 8319d 20h /or1k/tags/rel_5/or1200/
265 Modified virtual silicon instantiations. lampret 8322d 16h /or1k/tags/rel_5/or1200/
220 Fixed parameters in generic sprams. lampret 8333d 15h /or1k/tags/rel_5/or1200/
219 Fixed sensitivity list. lampret 8334d 17h /or1k/tags/rel_5/or1200/

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