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[/] [or1k/] [tags/] [rel_6/] [or1200/] [rtl/] - Rev 589

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Rev Log message Author Age Path
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8234d 05h /or1k/tags/rel_6/or1200/rtl/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8237d 07h /or1k/tags/rel_6/or1200/rtl/
571 Changed alignment exception EPCR. Not tested yet. lampret 8237d 16h /or1k/tags/rel_6/or1200/rtl/
570 Fixed order of syscall and range exceptions. lampret 8237d 18h /or1k/tags/rel_6/or1200/rtl/
569 Default ASIC configuration does not sample WB inputs. lampret 8238d 03h /or1k/tags/rel_6/or1200/rtl/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8238d 07h /or1k/tags/rel_6/or1200/rtl/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8244d 12h /or1k/tags/rel_6/or1200/rtl/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8248d 16h /or1k/tags/rel_6/or1200/rtl/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8249d 05h /or1k/tags/rel_6/or1200/rtl/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8279d 08h /or1k/tags/rel_6/or1200/rtl/
401 *** empty log message *** simons 8282d 18h /or1k/tags/rel_6/or1200/rtl/
400 force_dslot_fetch does not work - allways zero. simons 8282d 18h /or1k/tags/rel_6/or1200/rtl/
399 Trap insn couses break after exits ex_insn. simons 8282d 18h /or1k/tags/rel_6/or1200/rtl/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8285d 14h /or1k/tags/rel_6/or1200/rtl/
390 Changed instantiation name of VS RAMs. lampret 8285d 16h /or1k/tags/rel_6/or1200/rtl/
387 Now FPGA and ASIC target are separate. lampret 8285d 17h /or1k/tags/rel_6/or1200/rtl/
386 Fixed VS RAM instantiation - again. lampret 8285d 17h /or1k/tags/rel_6/or1200/rtl/
370 Program counter divided to PPC and NPC. simons 8289d 15h /or1k/tags/rel_6/or1200/rtl/
367 Changed DSR/DRR behavior and exception detection. lampret 8290d 04h /or1k/tags/rel_6/or1200/rtl/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8290d 23h /or1k/tags/rel_6/or1200/rtl/

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