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[/] [or1k/] [tags/] [rel_7/] - Rev 793

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793 Added synthesis off/on for timescale.v included file. lampret 8143d 15h /or1k/tags/rel_7/
792 Fixed port names that changed. lampret 8143d 15h /or1k/tags/rel_7/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8143d 15h /or1k/tags/rel_7/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8143d 15h /or1k/tags/rel_7/
789 Added response from memory controller (addr 0x60000000) lampret 8143d 16h /or1k/tags/rel_7/
788 Some of the warnings fixed. lampret 8143d 16h /or1k/tags/rel_7/
787 Added romfs.tgz lampret 8144d 10h /or1k/tags/rel_7/
786 Moved UCF constraint file to the backend directory. lampret 8144d 11h /or1k/tags/rel_7/
785 Added XSV specific documentation. lampret 8144d 11h /or1k/tags/rel_7/
784 Added soem missing files. lampret 8144d 11h /or1k/tags/rel_7/
783 Added sim directory and sub files/dirs. lampret 8144d 11h /or1k/tags/rel_7/
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8144d 11h /or1k/tags/rel_7/
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8144d 11h /or1k/tags/rel_7/
780 Added libraries. lampret 8144d 11h /or1k/tags/rel_7/
779 Added bench directory lampret 8144d 12h /or1k/tags/rel_7/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8144d 12h /or1k/tags/rel_7/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8144d 12h /or1k/tags/rel_7/
776 Updated defines. lampret 8144d 12h /or1k/tags/rel_7/
775 Optimized cache controller FSM. lampret 8144d 12h /or1k/tags/rel_7/
774 Removed old files. lampret 8144d 13h /or1k/tags/rel_7/

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