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[/] [or1k/] [tags/] [rel_7/] [or1200/] - Rev 1063

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Rev Log message Author Age Path
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7922d 16h /or1k/tags/rel_7/or1200/
1055 Removed obsolete comment. lampret 7954d 09h /or1k/tags/rel_7/or1200/
1054 Fixed a combinational loop. lampret 7954d 09h /or1k/tags/rel_7/or1200/
1053 Disabled cache inhibit atttribute. lampret 7954d 09h /or1k/tags/rel_7/or1200/
1040 Updated the script. lampret 7961d 14h /or1k/tags/rel_7/or1200/
1039 Added linter directory. lampret 7961d 14h /or1k/tags/rel_7/or1200/
1038 Fixed a typo, reported by Taylor Su. lampret 7961d 16h /or1k/tags/rel_7/or1200/
1037 First import of the new synopsys DC scripts. lampret 7961d 17h /or1k/tags/rel_7/or1200/
1036 Removed old synthesis scripts. lampret 7961d 17h /or1k/tags/rel_7/or1200/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7962d 06h /or1k/tags/rel_7/or1200/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7962d 16h /or1k/tags/rel_7/or1200/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7963d 06h /or1k/tags/rel_7/or1200/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7966d 11h /or1k/tags/rel_7/or1200/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7966d 13h /or1k/tags/rel_7/or1200/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7973d 10h /or1k/tags/rel_7/or1200/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7979d 09h /or1k/tags/rel_7/or1200/
993 Fixed IMMU bug. lampret 7979d 09h /or1k/tags/rel_7/or1200/
984 Disable SB until it is tested lampret 7982d 14h /or1k/tags/rel_7/or1200/
977 Added store buffer. lampret 7982d 16h /or1k/tags/rel_7/or1200/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7986d 06h /or1k/tags/rel_7/or1200/

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