OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_9/] - Rev 994

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8059d 16h /or1k/tags/rel_9/
993 Fixed IMMU bug. lampret 8059d 16h /or1k/tags/rel_9/
992 A bug when cache enabled and bus error comes fixed. simons 8060d 02h /or1k/tags/rel_9/
991 Different memory controller. simons 8060d 02h /or1k/tags/rel_9/
990 Test is now complete. simons 8060d 02h /or1k/tags/rel_9/
989 c++ is making problems so, for now, it is excluded. simons 8061d 10h /or1k/tags/rel_9/
988 ORP architecture supported. simons 8062d 01h /or1k/tags/rel_9/
987 ORP architecture supported. simons 8062d 08h /or1k/tags/rel_9/
986 outputs out of function are not registered anymore markom 8062d 09h /or1k/tags/rel_9/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8062d 21h /or1k/tags/rel_9/
984 Disable SB until it is tested lampret 8062d 21h /or1k/tags/rel_9/
983 First checkin lampret 8062d 23h /or1k/tags/rel_9/
982 Moved to sim/bin lampret 8062d 23h /or1k/tags/rel_9/
981 First checkin. lampret 8062d 23h /or1k/tags/rel_9/
980 Removed sim.tcl that shouldn't be here. lampret 8062d 23h /or1k/tags/rel_9/
979 Removed old test case binaries. lampret 8062d 23h /or1k/tags/rel_9/
978 Added variable delay for SRAM. lampret 8062d 23h /or1k/tags/rel_9/
977 Added store buffer. lampret 8062d 23h /or1k/tags/rel_9/
976 Added store buffer lampret 8062d 23h /or1k/tags/rel_9/
975 First checkin lampret 8062d 23h /or1k/tags/rel_9/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.