OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable/] [or1200/] - Rev 390

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
390 Changed instantiation name of VS RAMs. lampret 8246d 12h /or1k/tags/stable/or1200/
387 Now FPGA and ASIC target are separate. lampret 8246d 13h /or1k/tags/stable/or1200/
386 Fixed VS RAM instantiation - again. lampret 8246d 13h /or1k/tags/stable/or1200/
370 Program counter divided to PPC and NPC. simons 8250d 11h /or1k/tags/stable/or1200/
367 Changed DSR/DRR behavior and exception detection. lampret 8251d 00h /or1k/tags/stable/or1200/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8251d 19h /or1k/tags/stable/or1200/
360 Added OR1200_REGISTERED_INPUTS. lampret 8253d 11h /or1k/tags/stable/or1200/
359 Added optional sampling of inputs. lampret 8253d 11h /or1k/tags/stable/or1200/
358 Fixed virtual silicon single-port rams instantiation. lampret 8253d 12h /or1k/tags/stable/or1200/
357 Fixed dbg_is_o assignment width. lampret 8253d 12h /or1k/tags/stable/or1200/
356 Break point bug fixed simons 8253d 14h /or1k/tags/stable/or1200/
354 Fixed width of du_except. lampret 8254d 08h /or1k/tags/stable/or1200/
353 Cashes disabled. simons 8254d 18h /or1k/tags/stable/or1200/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8255d 21h /or1k/tags/stable/or1200/
351 Fixed some l.trap typos. lampret 8255d 23h /or1k/tags/stable/or1200/
350 For GDB changed single stepping and disabled trap exception. lampret 8256d 00h /or1k/tags/stable/or1200/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8260d 23h /or1k/tags/stable/or1200/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8260d 23h /or1k/tags/stable/or1200/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8262d 07h /or1k/tags/stable/or1200/
316 Fixed exceptions. lampret 8264d 05h /or1k/tags/stable/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.