URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] - Rev 340

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
340	Added hpint vector	lampret	8263d 05h	/or1k/tags/stable_0_1_0/
339	Added setpc test	lampret	8263d 05h	/or1k/tags/stable_0_1_0/
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8263d 05h	/or1k/tags/stable_0_1_0/
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8263d 05h	/or1k/tags/stable_0_1_0/
336	VAPI works	markom	8264d 00h	/or1k/tags/stable_0_1_0/
335	some small bugs fixed	markom	8264d 01h	/or1k/tags/stable_0_1_0/
334	removed vapi client file	markom	8264d 04h	/or1k/tags/stable_0_1_0/
333	small bug fixed	markom	8264d 07h	/or1k/tags/stable_0_1_0/
332	removed fixed irq numbering from pic.h; tick timer section added	markom	8264d 07h	/or1k/tags/stable_0_1_0/
331	dependecy is required by history analisis	markom	8264d 08h	/or1k/tags/stable_0_1_0/
330	Cache test	lampret	8264d 11h	/or1k/tags/stable_0_1_0/
329	Now using macros from spr_defs.h	lampret	8264d 11h	/or1k/tags/stable_0_1_0/
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8264d 13h	/or1k/tags/stable_0_1_0/
327	simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed.	lampret	8264d 13h	/or1k/tags/stable_0_1_0/
326	More realistic default cache type.	lampret	8264d 13h	/or1k/tags/stable_0_1_0/
325	minor ethernet testbench modifications	erez	8265d 16h	/or1k/tags/stable_0_1_0/
324	added initial ethernet RX simulation (very simple for now)	erez	8265d 16h	/or1k/tags/stable_0_1_0/
323	small fix	erez	8265d 16h	/or1k/tags/stable_0_1_0/
322	IC test repaired.C	simons	8265d 20h	/or1k/tags/stable_0_1_0/
321	added missing gdbcomm files	markom	8265d 23h	/or1k/tags/stable_0_1_0/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] - Rev 340

Filtering Options