OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] - Rev 584

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
584 This files are not ment to be here. simons 8212d 19h /or1k/tags/stable_0_1_0/
583 Several changes to make uclinux to work on xess board. simons 8212d 19h /or1k/tags/stable_0_1_0/
582 Several changes to make uclinux to work on xess board. simons 8212d 19h /or1k/tags/stable_0_1_0/
581 Several changes to make uclinux to work on xess board. simons 8212d 19h /or1k/tags/stable_0_1_0/
580 strsave changed to xstrdup markom 8213d 01h /or1k/tags/stable_0_1_0/
578 Insight markom 8213d 23h /or1k/tags/stable_0_1_0/
577 info spr fixed markom 8214d 18h /or1k/tags/stable_0_1_0/
576 some risc test added markom 8214d 19h /or1k/tags/stable_0_1_0/
575 Not needed to be compiled with -O2 optimization any more. simons 8214d 21h /or1k/tags/stable_0_1_0/
574 fixed some tests to work markom 8214d 23h /or1k/tags/stable_0_1_0/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8215d 03h /or1k/tags/stable_0_1_0/
572 Some new bugs fixed. simons 8215d 12h /or1k/tags/stable_0_1_0/
571 Changed alignment exception EPCR. Not tested yet. lampret 8215d 12h /or1k/tags/stable_0_1_0/
570 Fixed order of syscall and range exceptions. lampret 8215d 14h /or1k/tags/stable_0_1_0/
569 Default ASIC configuration does not sample WB inputs. lampret 8215d 23h /or1k/tags/stable_0_1_0/
568 include command added to cfg script markom 8216d 00h /or1k/tags/stable_0_1_0/
567 Commit lapsus fixed. simons 8216d 00h /or1k/tags/stable_0_1_0/
566 Fast sim switch fixed. simons 8216d 01h /or1k/tags/stable_0_1_0/
565 Regular update for new test cases. lampret 8216d 03h /or1k/tags/stable_0_1_0/
564 Updated test cases to use l.nop K instead of l.mtspr 0x1234 and l.sys 20x. lampret 8216d 03h /or1k/tags/stable_0_1_0/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.