OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] [gen_or1k_isa/] [sources/] [opcode/] - Rev 1765

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5572d 11h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1357 This commit was manufactured by cvs2svn to create tag 'stable_0_1_0'. 7060d 23h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7060d 23h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7062d 16h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1346 Remove the global op structure nogj 7075d 19h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7075d 20h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7075d 20h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1338 l.ff1 instruction added andreje 7091d 18h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1309 removed includes phoenix 7264d 13h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1308 Gyorgy Jeney: extensive cleanup phoenix 7267d 10h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7289d 10h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1286 Changed desciption of the l.cust5 insns lampret 7338d 13h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1285 Changed desciption of the l.cust5 insns lampret 7338d 13h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1169 Added support for l.addc instruction. csanchez 7651d 14h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1114 Added cvs log keywords lampret 7806d 06h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
1034 Fixed encoding for l.div/l.divu. lampret 7948d 07h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
879 Initial version of OpenRISC Custom Unit Compiler added markom 8013d 17h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
801 l.muli instruction added markom 8105d 20h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
722 floating point registers are obsolete; GPRs should be used instead markom 8133d 20h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/
720 single floating point support added markom 8134d 00h /or1k/tags/stable_0_1_0/gen_or1k_isa/sources/opcode/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.