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[/] [or1k/] [tags/] [stable_0_1_0/] [insight/] - Rev 1780

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Rev Log message Author Age Path
1765 root 5664d 11h /or1k/tags/stable_0_1_0/insight/
1357 This commit was manufactured by cvs2svn to create tag 'stable_0_1_0'. 7152d 23h /or1k/tags/stable_0_1_0/insight/
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7152d 23h /or1k/tags/stable_0_1_0/insight/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7154d 16h /or1k/tags/stable_0_1_0/insight/
1346 Remove the global op structure nogj 7167d 20h /or1k/tags/stable_0_1_0/insight/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7167d 20h /or1k/tags/stable_0_1_0/insight/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7167d 20h /or1k/tags/stable_0_1_0/insight/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7167d 21h /or1k/tags/stable_0_1_0/insight/
1338 l.ff1 instruction added andreje 7183d 18h /or1k/tags/stable_0_1_0/insight/
1333 gcc 3.4 compile fix phoenix 7198d 19h /or1k/tags/stable_0_1_0/insight/
1309 removed includes phoenix 7356d 14h /or1k/tags/stable_0_1_0/insight/
1308 Gyorgy Jeney: extensive cleanup phoenix 7359d 11h /or1k/tags/stable_0_1_0/insight/
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7381d 11h /or1k/tags/stable_0_1_0/insight/
1286 Changed desciption of the l.cust5 insns lampret 7430d 14h /or1k/tags/stable_0_1_0/insight/
1285 Changed desciption of the l.cust5 insns lampret 7430d 14h /or1k/tags/stable_0_1_0/insight/
1256 page size is 8192 on or32 phoenix 7515d 14h /or1k/tags/stable_0_1_0/insight/
1169 Added support for l.addc instruction. csanchez 7743d 14h /or1k/tags/stable_0_1_0/insight/
1152 *** empty log message *** phoenix 7823d 17h /or1k/tags/stable_0_1_0/insight/
1149 *** empty log message *** phoenix 7824d 06h /or1k/tags/stable_0_1_0/insight/
1144 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.		 sfurman 7826d 13h /or1k/tags/stable_0_1_0/insight/

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