URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] - Rev 12

Rev	Log message	Author	Age	Path
12	Added information to the section about how to configure and compile the package.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
11	Rebuild from configure.in.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
10	Support for both architectures. Specify architecture with the --target option.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
9	Added support for OpenRISC 100 and DLX.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
8	Initial revision.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
7	Major update of the enviorment. Now uses autoconf and automake. The simulator uses readline aswell to get input from the user. A number of new files added, some modified. The libc directory is now called support.	jrydberg	8883d 13h	/or1k/tags/stable_0_1_0/or1ksim/
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8884d 07h	/or1k/tags/stable_0_1_0/or1ksim/
5	Data and instruction cache simulation added.	lampret	8884d 07h	/or1k/tags/stable_0_1_0/or1ksim/
4	no message	lampret	8934d 11h	/or1k/tags/stable_0_1_0/or1ksim/
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9010d 00h	/or1k/tags/stable_0_1_0/or1ksim/