URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 13

Rev	Log message	Author	Age	Path
13	Rebuild of the generated files.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
12	Added information to the section about how to configure and compile the package.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
11	Rebuild from configure.in.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
10	Support for both architectures. Specify architecture with the --target option.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
9	Added support for OpenRISC 100 and DLX.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
8	Initial revision.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
7	Major update of the enviorment. Now uses autoconf and automake. The simulator uses readline aswell to get input from the user. A number of new files added, some modified. The libc directory is now called support.	jrydberg	8900d 03h	/or1k/tags/stable_0_2_0/
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8900d 21h	/or1k/tags/stable_0_2_0/
5	Data and instruction cache simulation added.	lampret	8900d 21h	/or1k/tags/stable_0_2_0/
4	no message	lampret	8951d 01h	/or1k/tags/stable_0_2_0/
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9026d 15h	/or1k/tags/stable_0_2_0/
1	Standard project directories initialized by cvs2svn.		9026d 15h	/or1k/tags/stable_0_2_0/