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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 1625

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Rev Log message Author Age Path
1625 First Import of uClinux for RC20x board jcastillo 6744d 08h /or1k/tags/stable_0_2_0/
1624 First Import of uClinux for RC20x board jcastillo 6744d 08h /or1k/tags/stable_0_2_0/
1623 First Import of uClinux for RC20x board jcastillo 6744d 09h /or1k/tags/stable_0_2_0/
1622 First Import of uClinux for RC20x board jcastillo 6744d 09h /or1k/tags/stable_0_2_0/
1621 First Impot jcastillo 6744d 10h /or1k/tags/stable_0_2_0/
1620 Added SMC91C111 LAN Chip Interruption to work with uClinux jcastillo 6749d 05h /or1k/tags/stable_0_2_0/
1619 Fixed types in function declaration jcastillo 6749d 10h /or1k/tags/stable_0_2_0/
1618 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6749d 17h /or1k/tags/stable_0_2_0/
1617 *** empty log message *** phoenix 6749d 17h /or1k/tags/stable_0_2_0/
1616 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6749d 17h /or1k/tags/stable_0_2_0/
1615 *** empty log message *** phoenix 6749d 17h /or1k/tags/stable_0_2_0/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6759d 18h /or1k/tags/stable_0_2_0/
1613 change default phoenix 6765d 03h /or1k/tags/stable_0_2_0/
1612 major optimizations for or32 target phoenix 6765d 04h /or1k/tags/stable_0_2_0/
1610 Update ChangeLog nogj 6768d 05h /or1k/tags/stable_0_2_0/
1609 0.2.0-rc2 release nogj 6768d 06h /or1k/tags/stable_0_2_0/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6769d 00h /or1k/tags/stable_0_2_0/
1607 Don't drop cycles from the scheduler nogj 6769d 00h /or1k/tags/stable_0_2_0/
1606 fix uninitialized reads phoenix 6769d 05h /or1k/tags/stable_0_2_0/
1605 Execute l.ff1 instruction nogj 6776d 00h /or1k/tags/stable_0_2_0/

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